Verilog Coding for Logic Synthesis

Provides a practical approach to Verilog design and problem solving.<br /> * Bulk of the book deals with practical design problems that design engineers solve on a daily basis.<br /> * Includes over 90 design examples.<br /> * There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.<br /> * Book is suitable for use as a textbook in EE departments that have VLSI courses